1. Field of the Invention
This invention generally relates to television receivers and, more particularly is directed to a multiple scanning type television receiver which is designed to be able to receive video signals having different line frequencies from a scanning converter and so on for doubling a line frequency in addition to the reception of the standard television broadcasting.
2. Description of the Prior Art
For example, in a television signal according to NTSC system, a video signal is composed of a vertical frequency of about 60 Hz and a horizontal line frequency of about 15.75 KHz. While, a scanning converter is proposed, which improves a reproduced picture quality by doubling the number of horizontal lines by means of calculating operation and so on. When this scanning converter is used, the video signal derived therefrom has a vertical frequency of around 60 Hz while a horizontal frequency of about 31.5 KHz.
Some computers of so-called high resolution display are designed to produce a video signal having a line frequency of about 24 KHz. Further, a so-called high definition television(HDTV) system is intended to employ a line frequency of about 33.75 KHz.
At present, a multiple scanning type television receiver has been proposed, which can commonly receive various video signals having different line frequencies with a single receiver.
An example of a multiple scanning type television receiver previously proposed by the assignee same as that of this application will be described with reference to FIGS. 1 to 6. FIG. 1 is a block diagram showing an overall of such multiple scanning type television receiver. Referring to FIG. 1, when receiving a standard video signal from a tuner for the standard television broadcasting, a video tape recorder, a video disc player, a tuner for the satellite broadcasting or some personal computers, etc., a video signal applied to an input terminal 1 is supplied through a video processing circuit 2 to an RGB processing circuit 3 and thereby three primary color signals R, G and B are formed. A video/RGB switching signal applied to another input terminal 4 is supplied to the RGB processing circuit 3 by which the video signal or RGB signals are selected and the three primary color signals are supplied through a video output circuit 5 to a cathode ray tube 6.
The video signal from the input terminal 1 is supplied to a sync. separator circuit 7 in which vertical and horizontal synchronizing signals are separated. The switching signal from the input terminal 4 is supplied to the sync. separator circuit 7 and the vertical synchronizing signal selected thereby from the video signal or RGB signals is supplied to a vertical deflection circuit 8. The vertical deflection signal from the vertical deflection circuit 8 is supplied to a vertical deflection yoke 9 of the cathode ray tube 6. The horizontal synchronizing signal derived from the sync. separator circuit 7 is supplied to an AFC(automatic frequency control) circuit 10 and to a mode detector circuit 11. The signal from the AFC circuit 10 is supplied to a horizontal oscillator circuit 12 and a normal control signal from the mode detector circuit 11 is supplied to the horizontal oscillator circuit 12. Then, the signal from the horizontal oscillator circuit 12 is supplied to a horizontal deflection circuit 13 and thereby a horizontal or line deflection signal derived from the horizontal deflection circuit 13 is supplied to a horizontal deflection yoke 14 of the cathode ray tube 6. The signal from the horizontal deflection circuit 13 is supplied to a high voltage generator circuit 15 which includes a flyback transformer(not shown). The high voltage produced in the high voltage generator circuit 15 is supplied to a high voltage terminal 16 of the cathode ray tube 6 and the flyback pulse therefrom is supplied to the AFC circuit 10.
A commercially available power from power supply terminals 17 is supplied to a power supply circuit 18 and the normal power supply voltage corresponding to the normal control signal from the mode detector circuit 11 is supplied from the power supply circuit 18 to the horizontal deflection circuit 13. The commercially available power from the power supply terminals 17 is supplied to another power supply circuit 19 and a stabilized power supply voltage therefrom is fed to other utilization circuits (not shown).
Thus, the standard or normal video signal is received and reproduced. Further, the previously proposed multiple scanning type television receiver can receive digital or analog primary color output signals of R, G and B(hereinafter simply RGB signals) from some high grade personal computers, so-called "CAPTAIN" (Character And Pattern Telephone Access Information Network) decoders, teletext decoders or scanning converters, etc. In this case, digital RGB signals are supplied to input terminals 20R, 20G and 20B and analog RGB signals are supplied to input terminals 21R, 21G and 21B, respectively. Then, one of them is selected by a switch 22 and then fed to the RGB processing circuit 3, in which the RGB signals are selected by the video/RGB switching signal from the input terminal 4 and fed to the video output circuit 5.
A digital synchronizing signal from an input terminal 20S and an analog synchronizing signal from an input terminal 21S are selected by a switch 23 and then fed to the sync. separator circuit 7, in which the selected signal is further selected by the switching signal from the input terminal 4 and fed to the vertical deflection circuit 8 and to the AFC circuit 10. The signal from the sync. separator circuit 7 is supplied to the mode detector circuit 11 in which the control signal having a voltage value proportional to the detected frequency is formed, and the control signal is supplied to the horizontal oscillator circuit 12, the horizontal deflection circuit 13 and to the power supply circuit 18, respectively.
Thus, the digital or analog RGB signals are received and reproduced on the cathode ray tube 6. Further, when a so-called superimposed reception in which the normal video signal and the RGB signals are mixed and then displayed is carried out, the switching signal applied to the input terminal 4 is made as an RGB mode signal. Also, a position control signal Ys for the superimposed picture and an area control signal Ym for the superimposed picture applied to an input terminal 24 are supplied to the RGB processing circuit 3, in which the video signal and the RGB signals are selectively switched by these signals Ys and Ym.
As described above, various video signals are received and reproduced. In the above television receiver, the horizontal deflection section is practically formed as follows. Referring to FIG. 2, the horizontal synchronizing signal from the sync. separator circuit 7 is supplied through a horizontal synchronizing signal input terminal 7H to a frequency-to-voltage converter(FVC) 31 which forms the mode detector circuit 11 and thereby a control voltage in proportion to the horizontal frequency is formed. The output voltage from the FVC 31 is supplied to one fixed terminal 32b of a switching circuit 32 and the other fixed terminal 32c of the switching circuit 32 is grounded via a reference voltage source 33. In this case, the voltage value of the reference voltage source 33 is set to be equal to the value of a voltage that the FVC 31 produces when the horizontal synchronizing signal having a line frequency of about 15.75KHz according to the NTSC system is supplied to the input terminal of the FVC 31. The switching circuit 32 is supplied at its control terminal with the video/RGB switching signal from the above-mentioned input terminal 4 through an input terminal 4a. Then, when the video/RGB switching signal is the video side switching signal, the movable contact arm 32a of the switching circuit 32 is connected to one fixed terminal 32c, while when the video/RGB switching signal is the RGB side signal, the movable contact arm 32a of the switching circuit 32 is connected to the other fixed terminal 32b. The voltage obtained at the movable contact arm 32a of the switching circuit 32 is supplied through a buffer amplifier 34 to a voltage controlled oscillator(VCO) 35 which forms a part of the horizontal oscillator circuit 12. The oscillating output from the VCO 35 is supplied through a drive circuit 36 to a switching transistor 37 which forms the horizontal deflection circuit 13.
The voltage obtained at the movable contact arm 32a of the switching circuit 32 is supplied through a control amplifier 38 to, for example, a Y-Z parametric type power supply circuit 39 which forms the power supply circuit 18. The output voltage from this power supply circuit 39 is fedback to the control amplifier 38 via a voltage divider 40 and thereby the output voltage is stabilized. This stabilized output voltage is supplied to the primary coil of a flyback transformer 41.
The switching transistor 37 is connected in series to the primary coil of the flyback transformer 41. A damper diode 42, a resonant condenser 43 and a series circuit formed of the horizontal yoke 14 and an S-shaping condenser (capacitor) 44 are respectively connected in parallel to the switching transistor 37.
The horizontal synchronizing signal is supplied to a detector circuit 45 which forms the AFC circuit 10 and the signal from a voltage divider 46 connected in parallel to the switching transistor 37 is supplied to the detector circuit 45 and thereby an AFC control signal is obtained therefrom. This AFC control signal is supplied through a low pass filter(LPF) 47 to the control terminal of the VCO 35.
Condensers (capacitors) 49 and 50 are connected in parallel to the resonant condenser 43 via a switching circuit 48, respectively. Condensers 52 and 53 are connected in parallel to the S-shaping condenser 44 via a switching circuit 51, respectively. The voltage from the FVC 31 is supplied to a comparator circuit 54 which produces a 3 value-output signal indicative of which one of the three frequency ranges of lower than 20 KHz, 20 to 30 KHz and higher than 30 KHz the frequency of the horizontal synchronizing signal belongs to. In response to the compared output from the comparator circuit 54, the switching circuits 48 and 51 are controlled such that both of two switches incorporated therein are turned off or either of them is turned on.
Accordingly, in this horizontal deflection section, the VCO 35 produces the oscillating signal having the frequency changing in a range from 15 to 34 KHz in synchronism with the input horizontal synchronizing signal thereby to carry out the horizontal deflection, while the power supply circuit 39 generates the voltage changing in a range from 58 to 123 Volts in proportion to the line frequency and thereby the amplitude of the horizontal deflection signal is made constant regardless of its frequency. The condensers 49, 50 and 52, 53 connected in parallel to the resonant condenser 43 and the S-shaping condenser 44 are selectively switched and according to the input horizontal frequency, correction of the characteristic is performed.
Further in the television receiver shown in FIG. 1, the vertical deflection section is practically constructed as follows. As shown in FIG. 3, the vertical synchronizing signal from the sync. separator circuit 7 is supplied through an input terminal 7V to a sawtooth wave oscillator 61 which forms a part of the vertical deflection circuit 8, by which a condenser 62, for example, is charged and discharged by the current from a current source 63 to form a vertical sawtooth wave. This sawtooth wave is supplied to a comparator circuit 64 which produces a 3 value-output signal which indicates a predetermined voltage region, a voltage region lower than the predetermined voltage and a voltage region higher than the predetermined voltage. This compared output is supplied to a control terminal of an up/down counter (U.D.C.) 65. The U.D.C. is supplied at its counting terminal with the vertical synchronizing signal. The counted value from the U.D.C. 65 is supplied to a D/A (digital-to-analog) converter (hereinafter simply D.A.C.) 66 and the current source 63 is controlled by the converted analog value from the D.A.C.
As a result, the sawtooth wave generator 61 generates, regardless of the frequency of the vertical synchronizing signal, a sawtooth wave the height of the wave (the amplitude) of which is controlled to fall in a predetermined voltage region. This sawtooth wave is supplied through a vertical output circuit 67 to the vertical deflection yoke 9. A series circuit formed of a condenser 68 and a resistor 69 is connected in series to the vertical deflection yoke 9 and a voltage divider 70 is connected in parallel to the resistor 69. The divided output from the voltage divider 70 is fedback to the vertical output circuit 67.
Thus, the amplitude of the vertical deflection signal is made constant regardless of its frequency. If one resistor, which forms a part of the voltage divider 70, is made variable, it is possible to control the amplitude of the vertical deflection signal to become a desired one.
Another set (formed of oscillator 71 to D.A.C. 76) of the circuit formed the same as the sawtooth wave oscillator 61 to D.A.C 66 is provided. The output value of the D.A.C 76 in this circuit is supplied to a pincushion correction signal forming circuit 77 and a vertical parabolic signal obtained at, for example, the connection point between the deflection yoke 9 and the condenser 68 is supplied to the pincushion correcting signal forming circuit 77 which forms a pincushion correction signal. The pincushion correction signal is delivered to a pin cushion correction circuit (not shown).
In the above mentioned television receiver, the necessary horizontal and/or vertical deflections are carried out in response to various horizontal and/or vertical frequencies and various video signals having different deflection frequencies are received and reproduced.
In the horizontal drive circuit 36 of such multiple scanning type television receiver, as shown in the extracted form of FIG. 4, a horizontal drive transistor 36a is driven by the oscillating signal(hereinafter called as the horizontal drive pulse) from the VCO 35, a horizontal drive transformer 36b is driven by the horizontal drive transistor 36a and an output switching transistor 37 of the horizontal deflection circuit 13 is driven by the secondary side of the horizontal transformer 36b.
On the other hand, in the standard or normal television receiver, it is designated such that the duty cycle of the oscillating signal from the VCO 35 is selected to be about 50% and the voltage +Vcc obtained at a power supply terminal 36c and the winding ratio of the horizontal drive transformer 36b, etc. are selected to operate the switching transistor 37 at an optimum driving condition.
If the duty cycle of the horizontal drive pulse of the VCO 35 is selected to be about 50%, no trouble occurs when the line frequency is fixed at about 15.75 KHz as in the normal television receiver. However, it was found out by us that some troubles such as misoperation may occur in the multiple scanning type television receiver as shown in FIGS. 1 to 4 which is supplied with the video signal having a horizontal or line frequency which may change to more than double of the standard frequency.
Referring to FIGS. 4 to 6, an explanation will be given on a case in which video signals having the line frequencies of 15 KHz and 30 KHz are received and reproduced under the condition that the duty cycle of the horizontal drive pulse from the VCO 35 is fixed at 50%.
When the line frequency is 15 KHz, a horizontal drive pulse as shown in FIG. 5A is supplied from the VCO 35 to the base of the horizontal drive transistor 36a and thereby the collector voltage and current of the horizontal drive transistor 36a become as shown in FIGS. 5B and 5C, respectively. Then, the base current of the output switching transistor 37 becomes as shown in FIG. 5D and the collector voltage of the output switching transistor 37 becomes as shown in FIG. 5E so that a deflection current such as shown in FIG. 5F flows through the horizontal deflection yoke 14.
In like manner, when the line frequency is 30 KHz, the voltage and current waveforms at the respective portions or corresponding to FIGS. 5A to 5F become as shown in FIGS. 6A to 6F, respectively. That is, since the peak-to-peak value of the deflection currents (shown in FIGS. 5F and 6F) flowing through the horizontal deflection yoke 14 has to be kept constant regardless of the change of the horizontal or line frequency, a storage time T.sub.S of the base current of the output switching transistor 37 and a retrace time T.sub.R of its collector voltage have to be kept constant, respectively (in FIGS. 5 and 6, the storage time of the output switching transistor 37 is constant and the storage time of the horizontal drive transistor 36b is zero for simplicity of description). For this reason, there may be a fear that when the line frequency becomes relatively high as shown in FIG. 6, a time point Ta (shown in FIG. 6D)at which the base current of the output switching transistor 37 begins to flow comes closer to an end time point Tb of a retrace pulse P.sub.R such as shown in FIG. 6E and dependent on the case, the base current will flow through the base of the output switching transistor 37.